fpga-lsp wires verible (SystemVerilog/Verilog) and
vhdl_ls (VHDL) into Claude Code as a native LSP plugin. Parse errors,
lint findings, go-to-definition, and hover for HDL files — surfaced to the agent
the moment they appear, no tool call, no MCP bridge.
sv-lint, sv-format, sv-diff..sv .svh .v .vh .vhd .vhdlRun these inside Claude Code. The Verible binary auto-installs into the plugin's data directory on first session.
On Linux x64, SystemVerilog and Verilog work immediately. VHDL requires
cargo install vhdl_ls and a project-root vhdl_ls.toml.
Other platforms get a one-line manual install.
Full install guide →
<= in always_ff; blocking = assignment to q creates a race.endmodule. Expected endmodule : counter.No new chat affordances. No new mental model. The editor knows what it knows and the agent reads it.
Parse errors and lint warnings appear automatically after every edit to .sv, .svh, .v, .vh, .vhd, .vhdl. The platform feeds them to the agent — no tool call.
Resolves module and signal symbols across files, driven by a resolved Verible filelist (project-owned if present, otherwise plugin-managed).
cross-fileType info and reference lists for SystemVerilog and VHDL identifiers, surfaced through the same LSP plumbing the editor already uses.
lsp-nativesv-lint, sv-format, sv-diff — stable wrappers around the matching Verible CLI tools, invocable directly or auto-picked by relevance.
sv-reviewer runs verible-verilog-lint first and cites Verible rule IDs as evidence, then layers HDL-specific judgment — inferred latches, blocking-in-always_ff, X-propagation, clock-domain hygiene.
SystemVerilog files run through verible-verilog-format on save via a PostToolUse hook. Quiet, fast, opinionated.
v1 ships one auto-install target. Other platforms get a clear error pointing at the manual install — never a generic "command not found".
| Platform | SV / Verilog | VHDL |
|---|---|---|
| Linux x64 | Auto-install | cargo |
| macOS | Manual | cargo |
| Windows | Manual | cargo |
| Linux arm64 | Manual | cargo |
Verible ships weekly. We pin so everyone on the same plugin version sees identical diagnostics and the LSP behaviour stays bounded for downstream projects.
| Verible | v0.0-4053-g89d4d98a |
| Linux x64 SHA256 | 1edc1f29c70d74213ed373e727183802d5a733e23f9ab9c74462f5b18b76f2c0 |
| vhdl_ls | cargo install vhdl_ls · pinned via Cargo.lock in your project |
| Bump cadence | Verible release bumped in a dedicated PR, ~quarterly. |
v1 is "done" against nyavana/pvz-fpga when the four success criteria pass end-to-end.
sv-lint, sv-format, sv-diff skills invocable.sv-reviewer agent that runs Verible lint first and cites rule IDs.slang-server opt-in (planned for v1.1 once dogfooding shows a need)..qsf, .xpr).veridian and svlangserver integrations — both stale upstream.fpga-flow — synthesis feedback (Yosys/Verilator/Quartus). Reserved for v2; placeholder README in v1.marketplace.json until manifest lands.